The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2024

Filed:

Apr. 20, 2022
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Purakh Raj Verma, Singapore, SG;

Su Xing, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/737 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66242 (2013.01); H01L 21/76898 (2013.01); H01L 23/5283 (2013.01); H01L 29/0649 (2013.01); H01L 29/737 (2013.01);
Abstract

A semiconductor structure includes following components. A first substrate has a first surface and a second surface opposite to each other. An HBT device is located on the first substrate and includes a collector, a base, and an emitter. A first interconnect structure is electrically connected to the base, located on the first surface, and extends to the second surface. A second interconnect structure is electrically connected to the emitter, located on the first surface, and extends to the second surface. A third interconnect structure is located on the second surface and electrically connected to the collector. An MOS transistor device is located on a second substrate and includes a gate, a first source and drain region, and a second source and drain region. Interconnect structures on the second substrate electrically connect the base to the first source and drain region and electrically connect the emitter to the gate.


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