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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12046657 B1

PDFFull Text
Date of Patent:
Jul. 23, 2024

Filed:

Oct. 21, 2020

Method of manufacturing a semiconductor device including capping layer, barrier layer and work function layer

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventor:

Hsueh Wen Tsau, Zhunan, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

Hauptman Ham, LLP

Primary Examiner:

David Chen

Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4983 (2013.01); H01L 21/28088 (2013.01); H01L 21/76846 (2013.01); H01L 21/823842 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01); H01L 29/7833 (2013.01); H01L 29/517 (2013.01);
Abstract

A method of making a semiconductor device includes forming first and second dummy gates over a substrate. The method includes removing the first and second dummy gates to define first and second openings. The method includes depositing a continuous gate dielectric layer in the first opening and the second opening. The method includes depositing a continuous capping layer on the gate dielectric layer, wherein the capping layer includes TaC. The method further includes depositing a continuous barrier layer on the capping layer, wherein the barrier layer includes TaC and a second material. The method includes depositing a first work function layer over the barrier layer in the first opening. The method includes depositing a second work function layer over the barrier layer in the second opening. The method includes depositing a continuous metal layer over each of the first work function layer and the second work function layer.

Find Patent Forward Citations

Tsau, Hsueh. (2024). Method of manufacturing a semiconductor device including capping layer, barrier layer and work function layer (U.S. Patent No. 12046657). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12046657

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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