The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2024

Filed:

Oct. 25, 2021
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Qiang Wan, Hefei, CN;

Kangshu Zhan, Hefei, CN;

Jun Xia, Hefei, CN;

Sen Li, Hefei, CN;

Penghui Xu, Hefei, CN;

Tao Liu, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/94 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/76 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0649 (2013.01); H01L 29/0692 (2013.01); H01L 29/1095 (2013.01); H01L 29/4236 (2013.01); H01L 29/42368 (2013.01);
Abstract

The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method includes: providing a base, wherein the base is provided with an active region; forming a gate layer on the base; forming isolation structures on a periphery of the gate layer, wherein in a direction away from the gate layer, each of the isolation structures at least includes a hollow portion and an isolation portion; forming an insulating structure on top surfaces of the isolation structures; forming contact plugs, wherein the contact plugs penetrate the insulating structure; an end of each of the contact plugs close to the base is electrically connected to the active region; each of the contact plugs is located on a side of each of the isolation structures away from the gate layer.


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