The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2024

Filed:

Aug. 30, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shu-Uei Jang, Hsinchu, TW;

Shih-Yao Lin, New Taipei, TW;

Chieh-Ning Feng, Taichung, TW;

Shu-Yuan Ku, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/823431 (2013.01); H01L 29/66545 (2013.01); H01L 29/6681 (2013.01); H01L 29/7851 (2013.01);
Abstract

A semiconductor device includes a substrate; a semiconductor fin structure disposed over the substrate, wherein the semiconductor fin structure extend along a first lateral direction; a gate structure that straddles a semiconductor fin structure, wherein the gate structure extends along a second lateral direction, the first lateral direction perpendicular to the second lateral direction; a dielectric fin structure that extends along the first lateral direction and is disposed next to the semiconductor structure fin structure; and a gate isolation structure disposed above the dielectric fin structure. The gate isolation structure contacts an upper portion of the gate structure at a first tilted interface.


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