The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2024

Filed:

Aug. 26, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Graziano Mirichigni, Vimercate, IT;

Andrea Martinelli, Bergamo, IT;

Christophe Vincent Antoine Laurent, Agrate Brianza, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/3287 (2019.01); G06F 1/28 (2006.01); G06F 1/3234 (2019.01); G11C 11/22 (2006.01); G11C 11/4096 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3287 (2013.01); G06F 1/28 (2013.01); G06F 1/3275 (2013.01); G11C 11/221 (2013.01); G11C 11/2259 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); G11C 11/4096 (2013.01);
Abstract

Methods, systems, and devices for bank-configurable power modes are described. Aspects include operating a memory device that has multiple memory banks in a first mode. While operating in the first mode, the memory device may receive a command to enter a second mode having a lower power consumption level than the first mode. The memory device may enter the second mode by switching a first subset of the memory banks to a first low power mode that operates at a first power consumption level and a second subset of the memory banks to a second low power mode that operates at a second power consumption level that may be lower than the first power consumption level. In some cases, the memory device may switch the first subset of memory banks from the first low power mode while maintaining the second subset of memory banks in the low power mode.


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