The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2024

Filed:

Dec. 07, 2020
Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventors:

Zhongwang Sun, Wuhan, CN;

Rui Su, Wuhan, CN;

Wenxi Zhou, Wuhan, CN;

Zhiliang Xia, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); G11C 8/14 (2006.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); G11C 8/14 (2013.01); H10B 43/10 (2023.02); H10B 43/35 (2023.02);
Abstract

A semiconductor device is provided. The semiconductor device includes a stack of word line layers and insulating layers that are stacked alternatingly over a substrate. The semiconductor device also includes a first dielectric trench structure. The first dielectric trench structure is positioned in a bottom select gate (BSG) layer of the word line layers to separate the BSG layer and extends in a first direction of substrate. The semiconductor device further includes a second dielectric trench structure. The second dielectric trench structure is positioned in a top select gate (TSG) layer of the word line layers to separate the TSG layer and extends in the first direction of the substrate. The second dielectric trench structure is offset from the first dielectric trench structure in a second direction of the substrate that is perpendicular to the first direction.


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