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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12040246 B1

PDFFull Text
Date of Patent:
Jul. 16, 2024

Filed:

Sep. 25, 2020

Chip-scale package architectures containing a die back side metal and a solder thermal interface material

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Susmriti Das Mahapatra, Tempe, AZ (US);

Malavarayan Sankarasubramanian, Chandler, AZ (US);

Shenavia Howell, Chandler, AZ (US);

John Harper, Chandler, AZ (US);

Mitul Modi, Phoenix, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Essential Patents Group, LLP

Primary Examiner:

Alonzo Chambliss

Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 21/48 (2006.01); H01L 21/50 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/36 (2006.01); H01L 23/373 (2006.01); H01L 23/42 (2006.01); H01L 23/488 (2006.01); H01L 21/60 (2006.01);
U.S. Cl.
CPC ...
H01L 23/36 (2013.01); H01L 21/4814 (2013.01); H01L 21/50 (2013.01); H01L 21/76838 (2013.01); H01L 23/367 (2013.01); H01L 23/3737 (2013.01); H01L 23/42 (2013.01); H01L 23/488 (2013.01); H01L 23/562 (2013.01); H01L 2021/60135 (2013.01);
Abstract

An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.

Find Patent Forward Citations

Das Mahapatra, Susmriti. (2024). Chip-scale package architectures containing a die back side metal and a solder thermal interface material (U.S. Patent No. 12040246). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12040246

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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