The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2024
Filed:
Aug. 10, 2022
Applicant:
Astera Labs, Inc., Santa Clara, CA (US);
Inventors:
Enrique Musoll, San Jose, CA (US);
Subbarao Arumilli, Cupertino, CA (US);
Anh T. Tran, Elk Grove, CA (US);
Assignee:
Astera Labs, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0802 (2016.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0802 (2013.01); G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01);
Abstract
A memory control device implements split storage of user-data and metadata components of a compound write data word, outputting the user-data component via a memory control interface for storage within an external memory subsystem while separately storing the metadata component within a metadata cache implemented within the memory control device.
Musoll, Enrique. (2024). Metadata-caching integrated circuit device (U.S. Patent No. 12032479). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12032479
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile