The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2024
Filed:
Jul. 27, 2022
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Yen-Chieh Huang, Changhua County, TW;
Hai-Ching Chen, Hsinchu, TW;
Yu-Ming Lin, Hsinchu, TW;
Chung-Te Lin, Tainan, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;
Abstract
A method for forming a semiconductor structure is provided. The method includes following operations. A layer stack is formed over the substrate. The formation of the layer stack includes the following sub-operations: a blocking layer is formed over the substrate, a lower conductive layer is formed over the blocking layer, a first seed layer is formed over the lower conductive layer, a ferroelectric layer is formed over the first seed layer, and an upper conductive layer is formed over the ferroelectric layer. The layer stack is patterned to form a gate stack over the substrate. A spacer layer is formed over sidewalls of the gate stack. A pattered interlayer dielectric layer is formed over the substrate and the gate stack. A source region and a drain region are formed in the substrate through the patterned interlayer dielectric layer.