The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2024

Filed:

Jul. 27, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Keng-Yao Chen, Hsinchu, TW;

Chang-Yun Chang, Taipei, TW;

Ming-Chang Wen, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/762 (2006.01); H01L 21/764 (2006.01); H01L 27/088 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823481 (2013.01); H01L 21/76224 (2013.01); H01L 21/764 (2013.01); H01L 21/823437 (2013.01); H01L 27/0886 (2013.01); H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/02274 (2013.01); H01L 21/0228 (2013.01);
Abstract

The embodiments described herein are directed to a method for mitigating the fringing capacitances generated by patterned gate structures. The method includes forming a gate structure on fin structures disposed on a substrate; forming an opening in the gate structure to divide the gate structure into a first section and a second section, where the first and second sections are spaced apart by the opening. The method also includes forming a fill structure in the opening, where forming the fill structure includes depositing a silicon nitride liner in the opening to cover sidewall surfaces of the opening and depositing silicon oxide on the silicon nitride liner.


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