The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2024

Filed:

Apr. 04, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;

Inventors:

Bo-Wen Hsieh, Miaoli County, TW;

Yi-Chun Lo, Zhubei, TW;

Wen-Jia Hsieh, Pusin Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 21/027 (2006.01); H01L 21/28 (2006.01); H01L 21/3213 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42376 (2013.01); H01L 21/0276 (2013.01); H01L 21/28088 (2013.01); H01L 21/32134 (2013.01); H01L 21/32139 (2013.01); H01L 29/4966 (2013.01); H01L 29/66492 (2013.01); H01L 29/66545 (2013.01); H01L 29/6659 (2013.01); H01L 29/66636 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01);
Abstract

A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.


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