The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2024

Filed:

Jun. 24, 2021
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Jonathan Almeria Noquil, Plano, TX (US);

Makarand Ramkrishna Kulkarni, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/16 (2023.01);
U.S. Cl.
CPC ...
H01L 25/16 (2013.01); H01L 23/3185 (2013.01); H01L 23/49822 (2013.01); H01L 23/49844 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/97 (2013.01);
Abstract

A multichip module (MCM) power package includes a multilayer routable leadframe substrate (MRLF) substrate including a first and a second RLF layer. A multilayer extending via extends from the first into the second RLF layer. A first vertical FET has a side flipchip attached to a bottom side of the second RLF. A second vertical FET has a side flipchip attached to a bottom side of the second RLF layer, and contacts the multilayer extending via. A controller integrated circuit (IC) is flipchip attached a top side of the MRLF substrate at least partially over the first vertical FET. A top mold compound is on a top side of the MRLF substrate lateral to the controller IC that is lateral to a metal pad on the multilayer extending via. A bottom side of the first and second vertical FET are exposed by a bottom mold compound layer.


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