The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 2024
Filed:
Jan. 31, 2022
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Chieh Lee, Hsinchu, TW;
Chia-En Huang, Hsinchu, TW;
Yi-Ching Liu, Hsinchu, TW;
Wen-Chang Cheng, Hsinchu, TW;
Yih Wang, Hsinchu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4091 (2006.01); G11C 5/06 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4091 (2013.01); G11C 5/063 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); H03K 19/20 (2013.01);
Abstract
A memory circuit includes first and second circuits. The first circuit includes a DRAM array including a plurality of bit lines, and the second circuit includes a computation circuit including a sense amplifier circuit. A boundary layer is positioned between the first and second circuits, and the boundary layer includes a plurality of via structures configured to electrically connect the plurality of bit lines to the sense amplifier circuit.