The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2024

Filed:

May. 05, 2021
Applicant:

Onto Innovation Inc., Wilmington, MA (US);

Inventors:

Kevin Eduard Heidrich, Beaverton, OR (US);

Nicholas James Keller, La Jolla, CA (US);

Assignee:

Onto Innovation Inc., Wilmington, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01N 21/956 (2006.01); G01N 21/21 (2006.01); G01N 21/95 (2006.01); G06F 30/3308 (2020.01); G06F 30/347 (2020.01);
U.S. Cl.
CPC ...
G01N 21/95607 (2013.01); G01N 21/211 (2013.01); G01N 21/9501 (2013.01); G06F 30/3308 (2020.01); G06F 30/347 (2020.01); G01N 2021/95615 (2013.01);
Abstract

Characteristics of a standard logic cell, e.g., a random logic cell, are determined using an effective cell approximation. The effective cell approximation is smaller than the standard logic cell and represents the density of lines and spaces of the standard logic cell. The effective cell approximation may be produced based on a selected area from the standard logic cell and include the same non-periodic patterns as the selected area. The effective cell approximation, alternatively, may represent non-periodic patterns in the standard logic cell using periodic patterns having a same density of lines and spaces as found in the standard logic cell. A structure on the sample, such as a logic cell or a metrology target produced based on the effective cell approximation is measured to acquire data, which is compared to the data for the effective cell approximation to determine a characteristic of the standard logic cell.


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