The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2024

Filed:

Jul. 15, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chih-Chuan Yang, Tainan, TW;

Kuo-Hsiu Hsu, Zhongli, TW;

Feng-Ming Chang, Zhubei, TW;

Kian-Long Lim, Hsinchu, TW;

Lien Jung Hung, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/785 (2013.01); H01L 27/0886 (2013.01); H01L 29/0665 (2013.01); H01L 29/16 (2013.01); H01L 29/41791 (2013.01); H01L 29/66545 (2013.01); H01L 29/6681 (2013.01); H01L 29/66818 (2013.01);
Abstract

A semiconductor device including nanosheet field-effect transistors (NSFETs) in a first region and fin field-effect transistors (FinFETs) in a second region and methods of forming the same are disclosed. In an embodiment, a device includes a first memory cell, the first memory cell including a first transistor including a first channel region, the first channel region including a first plurality of semiconductor nanostructures; and a second transistor including a second channel region, the second channel region including a semiconductor fin.


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