The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2024

Filed:

Jun. 08, 2022
Applicant:

Ventana Micro Systems Inc., Cupertino, CA (US);

Inventors:

John G. Favor, San Francisco, CA (US);

Michael N. Michael, Folsom, CA (US);

Vihar Soneji, Newark, CA (US);

Assignee:

Ventana Micro Systems Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 12/0875 (2016.01); G06F 12/1045 (2016.01);
U.S. Cl.
CPC ...
G06F 9/3806 (2013.01); G06F 12/0875 (2013.01); G06F 12/1045 (2013.01); G06F 2212/452 (2013.01); G06F 2212/6032 (2013.04);
Abstract

A microprocessor includes a branch target buffer (BTB). Each BTB entry holds a tag based on at least a portion of a virtual address of a block of instructions previously fetched from a physically-indexed physically-tagged set associative instruction cache using a physical address that is a translation of the virtual address, a translated address bit portion of a set index of an instruction cache entry from which the instruction block was previously fetched, and a way number of the instruction cache entry from which the instruction block was previously fetched. In response to a BTB hit based on a fetch virtual address, the BTB provides a translated address bit portion of a predicted set index that is the translated address bit portion of the set index from the hit on BTB entry and a predicted way number that is the way number from the hit on BTB entry.


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