The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2024

Filed:

Mar. 17, 2020
Applicant:

Mitsui Mining & Smelting Co., Ltd., Tokyo, JP;

Inventors:

Yoshinori Shimizu, Ageo, JP;

Hiroto Iida, Ageo, JP;

Misato Mizoguchi, Ageo, JP;

Akitoshi Takanashi, Ageo, JP;

Makoto Hosokawa, Ageo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/06 (2006.01); C23C 18/16 (2006.01); C23C 28/02 (2006.01); C25D 5/02 (2006.01); C25D 7/00 (2006.01); G03F 7/20 (2006.01); G03F 7/42 (2006.01);
U.S. Cl.
CPC ...
H05K 3/064 (2013.01); C23C 18/1646 (2013.01); C23C 18/1689 (2013.01); C23C 28/023 (2013.01); C25D 5/022 (2013.01); C25D 7/00 (2013.01); G03F 7/20 (2013.01); G03F 7/42 (2013.01); H05K 2203/072 (2013.01); H05K 2203/0723 (2013.01); H05K 2203/1152 (2013.01);
Abstract

There is provided a method for manufacturing a printed wiring board that effectively suppresses pattern failure and is also excellent in fine circuit forming properties. This method includes: providing an insulating substrate including a roughened surface; performing electroless plating on the roughened surface of the insulating substrate to form an electroless plating layer less than 1.0 μm thick having a surface having an arithmetic mean waviness Wa of 0.10 μm or more and 0.25 μm or less as measured in accordance with JIS B0601-2001 and a kurtosis Sku of 2.0 or more and 3.5 or less as measured in accordance with ISO 25178; laminating a photoresist on the surface of the electroless plating layer; performing exposure and development to form a resist pattern; applying electroplating to the electroless plating layer; stripping the resist pattern; and etching away an unnecessary portion of the electroless plating layer to form a wiring pattern.


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