The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2024

Filed:

May. 24, 2021
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Lars Liebmann, Mechanicsville, NY (US);

Jeffrey Smith, Clifton Park, NY (US);

Daniel Chanemougame, Niskayuna, NY (US);

Paul Gutwin, Williston, VT (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/06 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H10B 10/00 (2023.01);
U.S. Cl.
CPC ...
H01L 29/41733 (2013.01); H01L 27/0688 (2013.01); H01L 27/092 (2013.01); H01L 29/0665 (2013.01); H01L 29/41783 (2013.01); H01L 29/42392 (2013.01); H01L 29/78621 (2013.01); H10B 10/125 (2023.02); H10B 10/18 (2023.02);
Abstract

A semiconductor device includes a first device plane over a substrate. The first device plane includes a first transistor device having a first source/drain (S/D) region formed in an S/D channel. A second device plane is formed over the first device plane. The second device plane includes a second transistor device having a second gate formed in a gate channel which is adjacent to the S/D channel. A first inter-level connection is formed from the first S/D region of the first transistor device to the second gate of the second transistor device. The first inter-level connection includes a lateral offset from the S/D channel to the gate channel.


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