The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2024
Filed:
Aug. 02, 2021
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Eng Huat Goh, Ayer Itam, MY;
Wee Hoe, Bayan Lepas, MY;
Khang Choong Yong, Puchong, MY;
Ping Ping Ooi, Butterworth, MY;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); G06F 1/16 (2006.01); G06F 1/20 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/16 (2023.01); H01L 25/18 (2023.01); H05K 1/14 (2006.01); H05K 1/18 (2006.01); H05K 3/00 (2006.01); H05K 3/02 (2006.01); H05K 3/30 (2006.01); H05K 7/06 (2006.01); H05K 7/20 (2006.01);
U.S. Cl.
CPC ...
H01L 25/16 (2013.01); H01L 23/48 (2013.01); H01L 23/5386 (2013.01); H01L 25/065 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H05K 1/144 (2013.01); H05K 1/147 (2013.01); H05K 1/181 (2013.01); H05K 3/303 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15313 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19106 (2013.01); H05K 2201/048 (2013.01); H05K 2201/055 (2013.01); H05K 2201/1003 (2013.01); H05K 2201/10098 (2013.01); H05K 2201/10151 (2013.01); H05K 2201/10159 (2013.01); H05K 2201/10356 (2013.01); H05K 2201/10522 (2013.01); H05K 2201/10545 (2013.01); H05K 2201/10704 (2013.01); H05K 2201/10719 (2013.01); H05K 2201/10734 (2013.01);
Abstract
Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.