The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2024

Filed:

May. 16, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Huan Chen, Taoyuan, TW;

Kuo-Ching Hsu, New Taipei, TW;

Chen-Shien Chen, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49866 (2013.01); H01L 21/4846 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/81911 (2013.01); H01L 2224/81912 (2013.01);
Abstract

A chip package structure is provided. The chip package structure includes a first wiring substrate including a substrate, a first pad, a second pad, and an insulating layer. The chip package structure includes a nickel-containing layer over the first pad. The chip package structure includes a conductive protection layer over the nickel-containing layer. The conductive protection layer includes tin, and a recess is surrounded by the conductive protection layer and the insulating layer over the first pad. The chip package structure includes a chip over the second surface of the substrate. The chip package structure includes a conductive bump between the second pad and the chip.


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