The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2024
Filed:
Sep. 25, 2020
Intel Corporation, Santa Clara, CA (US);
Charles Henry Wallace, Portland, OR (US);
Mohit K. Haran, Hillsboro, OR (US);
Paul A. Nyhus, Portland, OR (US);
Gurpreet Singh, Portland, OR (US);
Eungnak Han, Portland, OR (US);
David Nathan Shykind, Buxton, OR (US);
Sean Michael Pursel, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.