The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2024

Filed:

Dec. 18, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Thomas Unterluggauer, Hillsboro, OR (US);

Alaa Alameldeen, Hillsboro, OR (US);

Scott Constable, Portland, OR (US);

Fangfei Liu, Hillsboro, OR (US);

Francis McKeen, Portland, OR (US);

Carlos Rozas, Portland, OR (US);

Anna Trikalinou, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2016.01); G06F 12/121 (2016.01); G06F 12/14 (2006.01);
U.S. Cl.
CPC ...
G06F 12/14 (2013.01); G06F 12/121 (2013.01); G06F 2212/1052 (2013.01);
Abstract

Techniques and mechanisms for a victim cache to operate in conjunction with a skewed cache to help mitigate the risk of a side-channel attack. In an embodiment, a first line is evicted from a skewed cache, and moved to a victim cache, based on a message indicating that a second line is to be stored to the skewed cache. Subsequently, a request to access the first line results in a search of both the victim cache and sets of the skewed cache which have been mapped to an address corresponding to the first line. Based on the search, the first line is evicted from the victim cache, and reinserted in the skewed cache. In another embodiment, reinsertion of the first line in the skewed cache includes the first line and a third line being swapped between the skewed cache and the victim cache.


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