The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 28, 2024
Filed:
May. 06, 2021
Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;
Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;
Fei Zhou, Shanghai, CN;
Abstract
A semiconductor structure and a method for forming the same are provided. One form of a method for forming a semiconductor structure includes: providing a base, the base including a first device region and a second device region, the base including an initial substrate and one or more initial channel stacks located on the initial substrate, and the initial channel stack including a sacrificial material layer and a channel material layer located on the sacrificial material layer; forming a discrete combined pattern on the initial channel stack, the combined pattern including a mandrel layer and a spacer layer located on a side wall of the mandrel layer, and the combined pattern exposing a boundary between the first device region and the second device region; forming a dielectric wall running through the initial channel stack at the boundary between the first device region and the second device region; and removing the mandrel layer. In embodiments and implementations of the present disclosure, the spacer layer has good uniformity, and the initial channel stack is etched by using the spacer layer as a mask to form a separate channel stack which has good morphology uniformity, which is conducive to improving the uniformity of the semiconductor structure performance.