The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2024

Filed:

May. 06, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chenchen Jacob Wang, Hsinchu, TW;

Chun-Chieh Lu, Taipei, TW;

Yi-Ching Liu, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 51/40 (2023.01); G11C 11/22 (2006.01); G11C 16/08 (2006.01); H01L 23/522 (2006.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01); H10B 51/20 (2023.01); H10B 43/10 (2023.01); H10B 51/10 (2023.01);
U.S. Cl.
CPC ...
H10B 51/40 (2023.02); G11C 11/2255 (2013.01); G11C 16/08 (2013.01); H01L 23/5226 (2013.01); H10B 43/27 (2023.02); H10B 43/40 (2023.02); H10B 51/20 (2023.02); H10B 43/10 (2023.02); H10B 51/10 (2023.02);
Abstract

Three-dimensional memories are provided. A three-dimensional memory includes a memory cell array, a first interconnect structure, a bit line decoder and a second interconnect structure. The bit line decoder is formed under the memory cell array and the first interconnect structure. The memory cell array includes a plurality of memory cells formed in a plurality of levels stacked in a first direction. The first interconnect structure includes at least one bit line extending in a second direction that is perpendicular to the first direction. The bit line includes a plurality of sub-bit lines stacked in the first direction. Each of the sub-bit lines is coupled to the memory cells that are arranged in a line in the corresponding level of the memory cell array. The second interconnect structure is configured to connect the bit line to the bit line decoder passing through the first interconnect structure.


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