The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2024

Filed:

Apr. 19, 2021
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chia-Hua Chang, Kaohsiung, TW;

Jian-Feng Li, Tainan, TW;

Hsiang-Chieh Yen, Penghu County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/15 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01);
U.S. Cl.
CPC ...
H01L 29/157 (2013.01); H01L 21/02458 (2013.01); H01L 21/02507 (2013.01); H01L 21/0254 (2013.01); H01L 21/30625 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01);
Abstract

The present disclosure provides a semiconductor device and a fabricating method thereof, the semiconductor device including a substrate, a nucleation layer, a buffer layer, an active layer and a gate electrode. The nucleation layer is disposed on the substrate, and the buffer layer is disposed on the nucleation layer, wherein the buffer layer includes a first superlattice layer having at least two heteromaterials alternately arranged in a horizontal direction, and a second superlattice layer having at least two heteromaterials vertically stacked along a vertical direction. The at least two heteromaterials stack at least once within the second superlattice layer. The active layer is disposed on the buffer layer, and the gate electrode is disposed on the active layer.


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