The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2024

Filed:

Aug. 09, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shu-Uei Jang, Hsinchu, TW;

Ya-Yi Tsai, Hsinchu, TW;

Ryan Chia-Jen Chen, Hsinchu, TW;

An Chyi Wei, Hsinchu, TW;

Shu-Yuan Ku, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28123 (2013.01); H01L 21/02164 (2013.01); H01L 21/32135 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823468 (2013.01); H01L 21/823481 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01);
Abstract

A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.


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