The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2024

Filed:

Oct. 16, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Adel A. Elsherbini, Chandler, AZ (US);

Georgios Dogiamis, Chandler, AZ (US);

Shawna M. Liff, Scottsdale, AZ (US);

Zhiguo Qian, Chandler, AZ (US);

Johanna M. Swan, Scottsdale, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/532 (2006.01); H01L 23/538 (2006.01); H01L 23/66 (2006.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 23/5329 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/66 (2013.01); H01L 24/17 (2013.01); H01L 2223/6627 (2013.01); H01L 2224/0237 (2013.01);
Abstract

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface, wherein the first die is embedded in a first dielectric layer, wherein the first surface of the first die is coupled to the second surface of the package substrate, and wherein the first dielectric layer is between a second dielectric layer and the second surface of the package substrate; a second die having a first surface and an opposing second surface, wherein the second die is embedded in the second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the package substrate by a conductive pillar; and a shield structure that at least partially surrounds the conductive pillar.


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