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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11984372 B1

PDFFull Text
Date of Patent:
May. 14, 2024

Filed:

Jul. 28, 2022

Integrated circuit package and method

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Teng-Yuan Lo, Hsinchu, TW;

Lipu Kris Chuang, Hsinchu, TW;

Hsin-Yu Pan, Taipei, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

Timor Karimy

Int. Cl.
CPC ...
H01L 23/24 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 23/24 (2013.01); H01L 21/4846 (2013.01); H01L 21/561 (2013.01); H01L 23/3135 (2013.01); H01L 23/3185 (2013.01); H01L 23/49827 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 24/97 (2013.01); H01L 25/0655 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/81815 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01);
Abstract

A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.

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