The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2024

Filed:

Oct. 19, 2021
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

BingYu Zhu, Hefei, CN;

Hai-Han Hung, Hefei, CN;

Yin-Kuei Yu, Hefei, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76877 (2013.01); H01L 21/76831 (2013.01); H01L 23/5223 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 28/60 (2013.01);
Abstract

The present application discloses a semiconductor structure. The semiconductor structure includes: a substrate, the substrate being provided with a conductive structure; a first lower electrode and a second lower electrode sequentially stacked, the first lower electrode being located between the second lower electrode and the substrate, and the first lower electrode being electrically connected to the conductive structure; a first dielectric layer and a first upper electrode, the first dielectric layer covering a sidewall surface of the first lower electrode, and the first upper electrode being located on one side of the first dielectric layer away from the first lower electrode; and a second dielectric layer and a second upper electrode, the second dielectric layer covering an inner wall and a bottom surface of the second lower electrode, and the second upper electrode filling the recess of the second lower electrode.


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