The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2024

Filed:

Mar. 04, 2022
Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventors:

Teng Chen, Hubei, CN;

Yan Wang, Hubei, CN;

Masao Kuriyama, Hubei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 7/06 (2006.01); G11C 7/12 (2006.01);
U.S. Cl.
CPC ...
G11C 7/106 (2013.01); G11C 7/06 (2013.01); G11C 7/1048 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 7/1087 (2013.01); G11C 7/12 (2013.01);
Abstract

The present disclosure provides page buffer circuits of 3D NAND devices. In some embodiments, the page buffer circuit comprises a first bit line segment sensing branch connected to a first bit line segment of a bit line, and a second bit line segment sensing branch connected to a second bit line segment of the bit line. The first bit line segment sensing branch and the second bit line segment sensing branch are parallel connected to a sensing node of the page buffer circuit. In some embodiments, the first bit line segment sensing branch comprises a first sense latch and a first bit line pre-charge path, and the second bit line segment sensing branch comprises a second sense latch and a second bit line pre-charge path.


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