Charge screening structure for spike current suppression in a memory array

Abstract

Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. Spike current suppression is implemented by charge screening structures. The charge screening structures are formed by laterally integrating insulating layers into selected interior regions of the left and/or right portions of the access line. The insulating layers vertically separate the access line into top and bottom conductive portions above and below the insulating layers. For memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the top or bottom conductive portion. During a spike discharge, charge is choked by this higher resistance path. This suppresses spike current that occurs when the memory cell is selected.