The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2024

Filed:

Aug. 08, 2021
Applicant:

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, CN;

Inventors:

Yu-Cheng Tung, Kaohsiung, TW;

Janbo Zhang, Zhangzhou, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H10B 12/0335 (2023.02); H01L 21/76831 (2013.01); H01L 21/76843 (2013.01); H01L 23/5226 (2013.01); H10B 12/315 (2023.02); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01);
Abstract

The present disclosure relates to a semiconductor device and a method of fabricating the same, which includes a substrate, a plurality of bit lines, a plurality of first plugs, a first spacer, a second spacer, a plurality of second plugs and a metal silicide layer. The bit lines are disposed on the substrate. The first plugs are disposed on the substrate and separated from the bit lines. The first spacer and the second spacer are disposed between each of the bit lines and the first plugs, and include a first height and a second height respectively. The second plugs are disposed on the first plugs respectively, and the metal silicide layer is disposed between the first plugs and the second plugs, wherein an end surface of the metal silicide layer is clamped between the second spacer and the first spacer.


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