The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2024

Filed:

Dec. 08, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Chen Zhang, Guilderland, NY (US);

Ruilong Xie, Niskayuna, NY (US);

Lan Yu, Voorheesville, NY (US);

Kangguo Cheng, Schenectady, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 27/088 (2013.01); H01L 29/41741 (2013.01); H01L 29/66666 (2013.01);
Abstract

Monolithically stacked VTFET devices having source/drain contacts with increased contact area and dielectric isolation are provided. In one aspect, a stacked VTFET device includes: at least a bottom VTFET below a top VTFET, wherein the bottom VTFET and the top VTFET each includes source/drain regions interconnected by a vertical fin channel, and a gate stack alongside the vertical fin channel; and source/drain contacts to the source/drain regions, wherein at least one of the source/drain contacts is in direct contact with more than one surface of a given one of the source/drain regions. A stacked VTFET device having at least a bottom VTFETbelow a top VTFET, and a bottom VTFETbelow a top VTFET, and a method of forming a stacked VTFET device are also provided.


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