The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2024
Filed:
Dec. 28, 2021
Sj Semiconductor (Jiangyin) Corporation, Jiangyin, CN;
Yenheng Chen, Jiangyin, CN;
Chengchung Lin, Jiangyin, CN;
SJ Semiconductor (Jiangyin) Corporation, Jiangyin, CN;
Abstract
The present disclosure provides a double-layer stacked 3D fan-out packaging structure and a method making the structure. The structure includes: a first semiconductor chip, a packaging material layer, a metal connecting pillar, a first rewiring layer, a second rewiring layer, a second semiconductor chip, solder ball bumps, and an underfill layer under the second semiconductor chip. The formed double-layer stacked 3D fan-out packaging structure is capable to package two sets of fan-out wafers in the three-dimension. A single package stacked up after die-cutting has two sets of chips in the third direction. The electrical signals of all chips in a single package can be controlled by arranging a first rewiring layer, a metal connecting post, and the second rewiring layer, so that more chips can be packaged in a single package, thus improving the package integration level and reducing the package volume.