The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2024

Filed:

Nov. 26, 2021
Applicant:

Yibu Semiconductor Co., Ltd., Shanghai, CN;

Inventor:

Weiping Li, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/5389 (2013.01); H01L 24/13 (2013.01); H01L 25/50 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01);
Abstract

A method of forming a package is provided. The method comprises assembling on a carrier a stack of chip layers including a plurality of first chip layers and a second chip layer; encapsulating the stack of chip layers in a molding compound; removing the carrier to form a package main body; forming a redistribution layer on an exposed side of a first chip layer; and dividing the package main body to form a plurality of packages. Each first chip layer includes first chips and chip couplers. A chip package includes at least one chip stack and at least one chip coupler stack on a singulated redistribution layer. Each chip stack includes at least one chip from each chip layer, and each chip coupler stack includes at least one chip coupler and/or at least one chip coupler segment from each of the first chip layers.


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