The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2024

Filed:

Mar. 12, 2020
Applicant:

Absolics Inc., Covington, GA (US);

Inventors:

Sungjin Kim, Suwanee, GA (US);

Youngho Rho, Daejeon, KR;

Jincheol Kim, Hwaseong-si, KR;

Byungkyu Jang, Suwon-si, KR;

Assignee:

Absolics Inc., Covington, GA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/46 (2006.01); H01L 23/15 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 23/15 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01);
Abstract

The embodiment relates to a packaging substrate and a semiconductor device, including an element unit including a semiconductor element; and a packaging substrate electrically connected to the element unit; and it applies a glass substrate as a core of the packaging substrate, thereby can significantly improve electrical properties such as a signal transmission rate by connecting the semiconductor element and a motherboard to be closer to each other so that electrical signals are transmitted through as short a path as possible. Therefore, it can significantly improve electrical properties such a signal transmission rate, substantially prevent generating of parasitic element, and simplify a process of treatment for an insulating layer, and thus provides a packaging substrate applicable to a high-speed circuit.


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