The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2024

Filed:

Nov. 04, 2020
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Praket Prakash Jha, San Jose, CA (US);

Shuchi Sunil Ojha, Redwood City, CA (US);

Jingmei Liang, San Jose, CA (US);

Abhijit Basu Mallick, Fremont, CA (US);

Shankar Venkataraman, San Jose, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/3205 (2006.01); H01L 21/3213 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H01L 21/76877 (2013.01); H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/31111 (2013.01); H01L 21/32055 (2013.01); H01L 21/32135 (2013.01); H01L 21/76802 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02);
Abstract

Exemplary methods of forming a semiconductor structure may include forming a first silicon oxide layer overlying a semiconductor substrate. The methods may include forming a first silicon layer overlying the first silicon oxide layer. The methods may include forming a silicon nitride layer overlying the first silicon layer. The methods may include forming a second silicon layer overlying the silicon nitride layer. The methods may include forming a second silicon oxide layer overlying the second silicon layer. The methods may include removing the silicon nitride layer. The methods may include removing the first silicon layer and the second silicon layer. The methods may include forming a metal layer between and contacting each of the first silicon oxide layer and the second silicon oxide layer.


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