The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2024

Filed:

Mar. 22, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Christophe Vincent Antoine Laurent, Agrate Brianza, IT;

Andrea Martinelli, Bergamo, IT;

Efrem Bolandrina, Fiorano al Serio, IT;

Ferdinando Bedeschi, Biassono, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/04 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0023 (2013.01); G11C 13/0004 (2013.01); G11C 13/003 (2013.01); G11C 2213/71 (2013.01);
Abstract

Methods, systems, and devices for shared decoder architecture for three-dimensional memory arrays are described. A memory device may include pillars coupled to an access line using two transistors positioned between the pillar and the access line. The gates of the two transistors may be coupled with respective gate lines coupled with circuitry configured to bias the gate line as part of an access operation for a memory cell coupled with the pillar. In some cases, the circuitry may be positioned between tiles of the memory device, at an end of one or more tiles of the memory device, between word line combs of a tile of the memory device, or a combination thereof.


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