The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2024

Filed:

Sep. 08, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruqiang Bao, Niskayuna, NY (US);

Ravikumar Ramachandran, Pleasantville, NY (US);

Barry Linder, Hastings-on-Hudson, NY (US);

Shahab Siddiqui, Clifton Park, NY (US);

Elnatan Mataev, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 29/40 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4966 (2013.01); H01L 29/401 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01);
Abstract

A first semiconductor device includes an interfacial layer over a substrate, a first high-κ dielectric layer over the interfacial layer, a second high-κ dielectric layer over the first high-κ dielectric layer, a Ti—Si mixing layer over the second high-κ dielectric layer, and a gate electrode layer over the Ti—Si mixing layer. A second semiconductor device includes an interfacial layer over a substrate, a first high-κ dielectric layer over the interfacial layer, a Ti—Si mixing layer over the first high-κ dielectric layer, a second high-κ dielectric layer over the Ti—Si mixing layer, and a gate electrode layer over the second high-κ dielectric layer. The method includes forming an interfacial layer over a substrate, forming a first high-κ dielectric layer over the interfacial layer, forming a second high-κ dielectric layer over the first high-κ dielectric layer, and forming a gate electrode layer over the second high-κ dielectric layer.


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