The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2024

Filed:

May. 05, 2021
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventor:

Fei Zhou, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7846 (2013.01); H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/30604 (2013.01); H01L 21/3086 (2013.01); H01L 21/76229 (2013.01); H01L 29/0653 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract

Semiconductor devices is provided. The semiconductor structure includes a semiconductor substrate having a middle region and an edge region adjacent to the middle region, a plurality of first fins formed on the middle region of the semiconductor substrate, a plurality of second fins formed on the edge region of the semiconductor substrate, a first adjustment layer formed on sidewall surfaces of the plurality of first fins and on the middle region of the semiconductor substrate, and an isolation structure formed on the semiconductor substrate and with a top surface lower top surfaces of the plurality of first fins and the plurality of second fins.


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