The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2024

Filed:

Nov. 10, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jihwan Suh, Suwon-si, KR;

Un-Byoung Kang, Hwaseong-si, KR;

Taehun Kim, Cheonan-si, KR;

Hyuekjae Lee, Hwaseong-si, KR;

Jihwan Hwang, Hwaseong-si, KR;

Sang Cheon Park, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 24/32 (2013.01); H01L 24/03 (2013.01); H01L 24/08 (2013.01); H01L 24/27 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/0346 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/32059 (2013.01); H01L 2224/3207 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/33181 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01); H01L 2225/06586 (2013.01);
Abstract

A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.


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