The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2024

Filed:

Aug. 21, 2023
Applicant:

Untether Ai Corporation, Toronto, CA;

Inventors:

Katsuyuki Sato, Tokyo, JP;

William Martin Snelgrove, Toronto, CA;

Saijagan Saijagan, Whitby, CA;

Joseph Francis Rohlman, Iowa City, IA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/418 (2006.01); G11C 11/4074 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01); G11C 11/412 (2006.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 11/418 (2013.01); G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); G11C 11/412 (2013.01); G11C 11/419 (2013.01);
Abstract

A static random-access memory is set forth comprising: a word line circuit for generating a word line signal on a word line; a plurality of six-transistor memory cells arranged between a first bitline, a second bitline and the word line for simultaneously selecting one of either all or a portion of the plurality of six-transistor memory cells for data reading or writing, and wherein each memory cell includes first and second n-channel transistors and a bitline precharge circuit for precharging the first bitline and second bitline to a voltage of Vdd/2 prior to the first and second n-channel transistors receiving the word line signal.


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