The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2024

Filed:

Jun. 22, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Yoshinori Fujiwara, Boise, ID (US);

Kevin G. Werhane, Boise, ID (US);

Jason M. Johnson, Boise, ID (US);

Daniel S. Miller, Boise, ID (US);

Assignee:

Micron Technolgy, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/133 (2014.01); G11C 11/4076 (2006.01); G11C 29/54 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G11C 29/54 (2013.01); H03K 5/133 (2013.01);
Abstract

A delay circuit is coupled to a memory device. At least a portion of the delay circuit is disposed in one or more memory banks on one or more memory chips of the memory device. The delay circuit is configured to calibrate an asynchronous signal received at each of the one or more memory banks so that the calibrated asynchronous signal has a common timing relationship with a respective internal command signal received at the corresponding memory bank for all of the one or more memory banks on the memory device. The calibrated asynchronous signals are used in various internal test operations to improve testing accuracy.


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