The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2024
Filed:
Sep. 26, 2020
Intel Corporation, Santa Clara, CA (US);
Mahesh Natu, Folsom, CA (US);
Anand K. Enamandram, Folsom, CA (US);
Manjula Peddireddy, Santa Clara, CA (US);
Robert A. Branch, Portland, OR (US);
Tiffany J. Kasanicky, Longmont, CO (US);
Siddhartha Chhabra, Portland, OR (US);
Hormuzd Khosravi, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Systems, methods, and apparatuses to implement spatially unique and location independent persistent memory encryption are described. In one embodiment, a system on a chip (SoC) includes at least one persistent range register to indicate a persistent range of memory, an address modifying circuit to check if an address for a memory store request is within the persistent range indicated by the at least one persistent range register, and append a unique identifier value, for a component corresponding to the memory store request for the address, to the address to generate a modified address and output the modified address as an output address when the address is within the persistent range, and output the address as the output address when the address is not within the persistent range, and an encryption engine circuit to generate a ciphertext based on the output address.