The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2024

Filed:

Dec. 16, 2021
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventor:

Fei Zhou, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 10/00 (2023.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H10B 10/12 (2023.02); H01L 27/0924 (2013.01); H01L 29/0847 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A semiconductor device is provided. The semiconductor device includes: a substrate and first gate structures and source/drain doped layers on the substrate. Each of the source/drain doped layers is located at two sides of one first gate structure. The semiconductor device further includes a dielectric layer on the substrate. The dielectric layer contains first grooves, exposing the source/drain doped layers, wherein each first groove includes a first-groove bottom part and a first-groove top part located above the first-groove bottom part, and a size of the first-groove top part is larger than a size of the first-groove bottom part. The semiconductor device further includes a first conductive structure located in the first-groove bottom part, an insulating layer located in the first-groove top part and on the first conductive structure, and a second conductive structure located in the dielectric layer and connected to the first gate structure.


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