The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2024

Filed:

Oct. 24, 2021
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chih-Kai Hsu, Tainan, TW;

Ssu-I Fu, Kaohsiung, TW;

Yu-Hsiang Hung, Tainan, TW;

Wei-Chi Cheng, Kaohsiung, TW;

Jyh-Shyang Jenq, Pingtung County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/08 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0847 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/42356 (2013.01); H01L 29/42368 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/78 (2013.01); H01L 29/7833 (2013.01); H01L 29/7848 (2013.01); H01L 29/785 (2013.01); H01L 29/665 (2013.01);
Abstract

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.


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