The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2024

Filed:

Feb. 05, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Ryota Suzuki, Sagamihara, JP;

Hirokazu Matsumoto, Hachioji, JP;

Makoto Sato, Sagamihara, JP;

Assignee:

MICRON TECHNOLOGY, INC., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); H01L 29/42376 (2013.01);
Abstract

Apparatuses including semiconductor layout to mitigate local layout effects are disclosed. An example apparatus includes a plurality of standard cells each including an active region, an isolation region adjacent the active region, and a first gate structure disposed on the active region and the isolation region. The first gate structure includes a first gate portion disposed on the active region, and a first contact portion disposed on the isolation region. The apparatus further includes a second gate structure disposed on the active region and the isolation region. The second gate structure includes a second gate portion disposed on the active region, and a second contact portion disposed on the isolation region. In the apparatus, a distance between a first contact point and the first gate portion is substantially equal to a distance between a second contact point and the second gate portion.


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