The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2024

Filed:

May. 16, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kristof Darmawikarta, Chandler, AZ (US);

Srinivas V. Pietambaram, Chandler, AZ (US);

Hongxia Feng, Chandler, AZ (US);

Xiaoying Guo, Chandler, AZ (US);

Benjamin T. Duong, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/66 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/66 (2013.01); H01L 21/76825 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 21/76879 (2013.01); H01L 23/5283 (2013.01); H01L 23/53233 (2013.01); H01L 23/53238 (2013.01); H01L 2223/6605 (2013.01);
Abstract

Conductive structures in a microelectronic package and having a surface roughness of 50 nm or less are described. This surface roughness is from 2 to 4 times less than can be found in packages with conductive structures (e.g., traces) formed using alternative techniques. This reduced surface roughness has a number of benefits, which in some cases includes a reduction of insertion loss and improves a signal to noise ratio for high frequency computing applications. The reduced surface roughness can be accomplished by protecting the conductive structure r during etch processes and applying an adhesion promoting layer to the conductive structure.


Find Patent Forward Citations

Loading…