The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2024

Filed:

Aug. 14, 2019
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventor:

Li Hong Xiao, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/31 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/306 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 21/0214 (2013.01); H01L 21/02164 (2013.01); H01L 21/02636 (2013.01); H01L 21/30604 (2013.01); H01L 21/31116 (2013.01); H01L 21/7682 (2013.01); H01L 29/40117 (2019.08);
Abstract

Embodiments of methods to form three-dimensional (3D) memory devices include the following operations. First, an initial channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset is formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel is formed by filling the channel hole with a channel-forming structure, the semiconductor channel having a memory layer including a plurality of first memory portions each surrounding a bottom of a respective second layer and a plurality of second memory portions each connecting adjacent first memory portions.


Find Patent Forward Citations

Loading…