The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2024

Filed:

Jul. 30, 2021
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Gongyi Wu, Hefei, CN;

Youquan Yu, Hefei, CN;

Yong Lu, Hefei, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/401 (2013.01); H01L 21/28247 (2013.01); H01L 29/49 (2013.01);
Abstract

A method for manufacturing a semiconductor structure includes the following operations. A first conductive layer, a second conductive layer and a passivation layer are successively formed on a semiconductor substrate. The passivation layer and the second conductive layer are patterned to form a primary gate pattern. A portion of the first conductive layer that is not covered by the primary gate pattern, is exposed. The primary gate pattern is subjected with plasma treatment to form a first protective layer. A dielectric layer is formed. The exposed portion of the first conductive layer is removed to retain a portion of the first conductive layer covered by the primary gate pattern. A second protective layer is formed on a side wall of the exposed portion of the first conductive layer.


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